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Altera_Forum's avatar
Altera_Forum
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14 years ago

SGDMA write_waitrequest always 'high'

Hello everyone, In order to achieve my project, I have to use my Nios II in order to send data from my FPGA to a server. My FPGA will have to read data from a Dual port Onchip memory which is c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I think that I found the reason why my ready signal was always low even when I attempted everything you said. I put descriptor_read/write signal of my Qsys file on the wrong memory.

I linked the descriptor_read/write to my DDR3 where the .heap and .data is stored and now the ready signal is working fine.

I still don't know whether my SGDMA is working or not but the ready signal is high ^^

Thank you again BadOmen.

Hopefully it was a stupid error again which can be easily fixed =)