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Altera_Forum
Honored Contributor
Honored ContributorSGDMA write_waitrequest always 'high'
Hello everyone, In order to achieve my project, I have to use my Nios II in order to send data from my FPGA to a server. My FPGA will have to read data from a Dual port Onchip memory which is c...
Altera_ForumHonored Contributor
Honored ContributorBest kinds of mistakes to make are the simple ones since they are the easiest to fix :)
I would recommend modifying that streaming core providing data to the SGDMA since it's not adhering to the ST spec. The data, sop/eop, empty, etc... signals should be held constant when valid is high but ready is low.
