Hi, I just started to learn using sgdma to transfer data from DDR2. I have the sopc attached and please give me some idea if that is correct. Another issue is that I do not understand how dma communicate between Nios and hardware. I used to use PIO and IOWR and the data is shown on the pio pin. However, I am not able to find some pin related to this dma. Should I add some other component such as fifo? Please give me some hint on this. Thanks

I would highly recommend using the HDL driver that comes with the SGDMA. You can find the APIs in the SGDMA user guide.

Hi BadOmen, Thanks a lot for your advice. But could you please go in more details about it? I have read the document and the sgdma seems working through the program below. But still how can I send the data to the hardware? Should I wire some pio to the sgdma? If possible can you show me some diagram/function call to get the data back to the hardware? Thanks! This is the program: int main() { int i; // int timeout=0; for (i=0;i<1000;i++) // buf initialization buf[i]=i%256; desc=(alt_sgdma_descriptor *)ONCHIP_MEM_BASE; // redefine the base address ? // ***************** open sgdma_tx ********************// sgdma_tx_dev=alt_avalon_sgdma_open(SGDMA_TX_NAME); if(!sgdma_tx_dev) { printf("ERROR: can't open TX SGDMA"); return -1; } // ***************** open sgdma_rx ********************// sgdma_rx_dev=alt_avalon_sgdma_open(SGDMA_RX_NAME); if(!sgdma_rx_dev) { printf("ERROR: can't open RX SGDMA"); return -1; } // ***************** reset RX SGDMA ********************// IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_RX_BASE,ALTERA_AVALON_SGDMA_CONTROL_SOFTWARERESET_MSK); IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_RX_BASE,0x0); // ***************** reset TX SGDMA ********************// IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_TX_BASE,0); // Why these two are different here? IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_TX_BASE,0xFF); // ***************** register rx callback ********************// alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) &sgdma_rx_isr, // ? (alt_u16) ALTERA_AVALON_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK, 0 ); // ***************** construct a descriptor for ST to MM transfer ********************// alt_avalon_sgdma_construct_stream_to_mem_desc( &desc[0], &desc[1], rx_payload, 0, 0 ); // ***************** construct a descriptor for MM to ST transfer ********************// alt_avalon_sgdma_construct_mem_to_stream_desc( &desc[2], &desc[3], (unsigned int*) buf, (256), 0, 1, 1, 0 ); // ***************** start sgdna_rx ********************// alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, &desc[0]); // ***************** start sgdna_tx ********************// alt_avalon_sgdma_do_sync_transfer(sgdma_tx_dev, &desc[2]); }

Hi BadOmen, I modified the sopc. One pio is added to get the data. Is that what you mean by wire dma to PIO? If so, could you let me know which api I should use to transmit the data to that pio? Thanks!

Why don't you connect tx/rx to ddr and look like my easy to test. Use the main.c (rename .doc to .c) program I include and give a try. Sean

I would use the "DMA" and not the "SGDMA" The DMA is much easier to work with. The only reason for using the SGDMA is if you want the DMA engine to start working on another transfer immediately after completing another bulk data transfer. Both of those DMAs have HAL drivers so you don't have to worry about accessing the DMA hardware directly, that's the purpose of the software driver.

SGDMA data output issue | Altera Community

16 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
This is starting to sound like using a PIO would be a bad idea. If for example the memory holding the data becomes blocking you might have an idle cycle between accesses to the PIO. Sounds more like FIFOs would be your best best with the DMA operating faster than the FIFOs can be drained to protect against underflow.

While you are looking at DMAs you might want to evaluate this one: http://www.alterawiki.com/wiki/modular_sgdma It's a SGDMA only with a much simplier programming model (to software it looks like the regular DMA with a FIFO buffering descriptors internally).
--- Quote End ---

Yeah it seems to me that pio is not a good idea. The project is about some data transferring to DDR2,stay for a while, and get it back with a speed of around 1Gbps. So you think I should use DMA along with the FIFO?

Looking forward to your suggestion
Altera_Forum
Honored Contributor
14 years ago
sgdma is best then dma or FIFO. I also have program for dma too.

Sean
Altera_Forum
Honored Contributor
14 years ago
Hi sean,

I agree with you. So now the problem leaves to how to get the data in and out of Nios...Do you have ay suggestions?

Thanks!
Altera_Forum
Honored Contributor
14 years ago
I don't know what do you mean get data in and out?

In Nios IDE, to use IOWR/IORD --- write/read.

Sean
Altera_Forum
Honored Contributor
14 years ago
Hi sean,

Sorry I did not make it clear. Let;s refer to the sopc and main.c you show me. The data is already in Nios, right? (alt_u32 create_test_data). Now my case is I have the data outside Nios, which is the output of some verilog module. My question is how to import these data into Nios instead of generate inside Nios?

Thanks!
Altera_Forum
Honored Contributor
13 years ago
Hi Bingomickey,
I'm having the same kind of trouble and I wanted to know if you managed to send your data from your hardware into your SOPC Nios component?

In my case I want to send data from my Nios to my hardware component.
I'm thinking about using multiple PIO with several FIFO but I dread that the latency may be too long.

Thank you in advance!

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SGDMA data output issue

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