SGDMA behaves badly if its descriptors are in off-chip RAM?

Unfortunately, I changed the QSYS code around to use on-chip descriptors only. Is it important to know these details in terms of understanding the situation? I am under some schedule pressure at the moment, but when I return from travel I might be able to grab the details you requested.

There were not any timing violations in the code in question other than a very slim margin for an RGMII interface between chips; I am fixing that now, to run at a lower clock rate.

It could be that my issues was due to programmer error, but the signal tap did appear to be quite odd so I decided to document the situation. Could this be caused by a configuration error on the avalon stream? In this case it was a direct connection between the TSE MAC and the SGDMA.

Thanks for your attention to the matter,