Seriallite II simulation no EOP

Hi anand,

Thanks for replying

For Arria V devices, such as mine The auto generated testbench produced by Quartus 18.1 does does not compile :

"The Configure Transceiver page is disabled when you select Arria V, Cyclone V, or Stratix V as the target device family. To add a transceiver, you are required to instantiate the Custom PHY IP core."

I hope the way i connected them is ok, since there is no real reference for this (only applicable example is stratix iv on quartus 12, which has totally different pins).

Because of this, the generated test-bench is correct the same way my design is correct 😥

I will try to attach my the relevant files.

Regards

Oded