Forum Discussion
host
Occasional Contributor
Occasional ContributorSerial Lite III "start_of_burst" and "end_of_burst"
I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
It okay to have discontinuous valid. You cannot tie these to GND.
Please refer to the 5.8. User Data Interface Waveforms (intel.com)
This will help you to understand in detail.
Thank you,
Kshitij Goel
hostOccasional Contributor
Occasional ContributorIf my data isn't really segmented into packets , do I have to assert the "end of burst" signal EVERY TIME that I de-assert valid ?
If I don't - doesn't this mean that I can simply tie it to GND ?
