Sections missing from fPLL documentation
As far as I can tell, there is no dedicated documentation for fPLLs (e.g. in Cyclone 10 GX and Arria 10). Therefore, I am forced to use the limited scraps of information scattered around the Transceiver PHY user guides.
The Cyclone 10 GX Transceiver PHY User Guide is especially lacking. Section 3.1.3 looks somewhat similar to that section in the Arria 10 Transceiver PHY User Guide, except sections 3.1.3.1 ("Instantiating the fPLL IP Core") and 3.1.3.2 ("fPLL IP Core") are mysteriously missing.
Should I assume the Arria 10 sections apply also to Cyclone 10 GX? This seems like an altogether unsafe assumption, as there are many subtle differences between the two device families.
Needless to say, I am absolutely shocked by the state of the Intel FPGA documentation in general. It is an absolute mess. I have wasted many days of effort as a direct result of Intel's disorganized and incomplete documentation.