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VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SDRAM Throughput problems using Arria 10 SOC

HI, I was doing a test on Arria 10 soc board regarding fsdram0 and fsdram1 bus speed test using msgdma but I am facing the problem as follows: For fpga fabric 100MHz clock I got a write speed of 8....
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

  1. Regarding changing DDR3 freq from 600MHz to 750MHz doesn't increase the BW
  • Byright you should see some improvement on BW.
    • Dummy question - just to ensure you also change your on board clock source to pump in the correct frequency to PLL refclk pin to boost DDR3 frequency to 750MHz, right ?
  1. Factor affecting the efficiency
  • Your data path transfer need to pass through a lot of design block before it can reach DDR3 IP like your user logic design, dma IP, SDRAM L3 interconnect
    • Any efficiency drop in any of this design block may affect your overall BW. The bottleneck can be anywhere. You can look into your design to see if you can optimize your design further.
    • For DDR3 IP wise, the main factor will be refresh control and also addressing access (sequential will be better than random)

Thanks.

Regards,

dlim