SDRAM Controller

CH...

If you need something more graphical in nature to help you to understand the state machine switches you could go ahead and compile the design without connecting your top level SOPC Builder project i/o pins, and then use the Quartus graphical state machine viewer to study the behavior.

I am not sure what you hope to gain other than knowledge for knowledge sake. I don't know your level of knowledge, so forgive me if I insult you; but generally speaking, the state machines handle init cycles, precharge, and refresh commands, as well as placing the needed cs_n, ras_n, cas_n, & wr_n on the bus. This information is used in connection with the row, bank and column addresses to locate the storage position in sdram. There are many documents on this suject including the datsheet of the chip you are using that will provide you with their specific timimg requirements for parameterization of your controller module. Also, if you plan to use the pll to generate your external clock, I would suggest you start with a phase delay of -4ns for a custom board and work from there...agian all in the manual.

By the way, what is you preferred design flow? Are you aware that you can create a schematic, and use generated symbols to make your design visually? I have found that method beneficial at times over the homogenous verilog/VHDL approach.

--Daniel