New ContributorHi,
I am looking for SDI II multi-rate multi Tx instances for C10 GX.
I followed the information on the UG-01125 and add the commands in the qsf.
"set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to sdi_tx[0] -entity top"
"set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to sdi_tx[1] -entity top"
But the fitter reported error as attachment.
Please help me solve this problem.
Thank you!
BRs,
Bin
Regular ContributorHi,
As I understand it, you observed some errors when trying to merge the reconfiguration interfaces for simplex instances. For your information, the XCVR_RECONFIG_GROUP assignment is to merge two simplex TX and RX into the one physical transceiver channel. For example, in your design, you have one TX only instance and one RX only instance. By using this assignment, you can merge them into a single transceiver channel to save resource provided all the requirements in Intel Cyclone 10 GX Transceiver PHY User Guide -> "Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores" are met.
I notice that you are assigning the XCVR_RECONFIG_GROUP to two TX instances. Note that the same group is for one TX and one RX. You may refer to Intel Cyclone 10 GX Transceiver PHY User Guide -> "Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores" for further details.
Please let me know if there is any concern. Thank you.
Best regards,
New ContributorHi CheePin,
Thank you for the reply.
Now I see the assignment is for 1 Tx with 1 Rx..
Then if I need to have multiple instances in the same transceiver bank, where I can find reference data?
Thank you!
BRs,
Bin
Regular ContributorHi Bin,
Thanks for your update. Yes, your understanding is correct, the assignment is to fit 1 TX only instance and 1 RX only instance into the one physical transceiver channel. If you have multiple TX only and RX only instances, then you will need to set the assignment to each pair with different reconfig group number. You would need to decide which pair of instances to fit into which transceiver channel.
Please let me know if this answer your inquiry. If not, please help to further elaborate your inquiry. Thank you.
New ContributorHi Chee_Pin,
My goal now is to fit Quad-SDI Tx and Rx into a bank in C10 GX.
I looked the example generated by the IP core.
The Tx design didn't include any reconfiguration logic.
Instead it just had transceiver phy, sdi ip, reset controller and fPLL.
Then for a Quad "bonding" design, I might need to have all 4-channels share the same fPLL and reset controller ?
Otherwise if I followed the reference, I need to have 4 fPLLs, the resource is not enough..
Am my understanding correct?
For the Rx side, I saw reconfiguration in the reference.
Then how could I implement a Quad SDI Rx ?
Or where I can find related information ?
Thank you!
Best Regards,
Bin
Regular ContributorHi,
Based on my understanding, generally the SDI channels will be non-bonded. Therefore, in the example design, you will see independent TX/RX/Duplex. In the cases where you do not have enough fPLL, probably you could look into using other TX PLL ie ATX PLL to see if it helps. If not, you might need to look for a device with more XCVR banks. Alternatively, you can also try to share single fPLL/reset controller for all the TXs. Not that doing so, you would not be able to reset the TX individually.
For the SDI RX, you may instantiate 4 RX instances separately.
It is recommended for you to refer to the C10GX XCVR PHY user guide -> "Rules for Merging Reconfiguration Interfaces Across Multiple IP Cores" for the requirement to merge. You can start with one TX + one RX. Then slowly increase the number of pairs.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Regular ContributorHi,
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
