SDI II IP - TX sync Issue

Hi SK Lim,

There is a VCXO on my board. I connected this frequency (148.5Mhz) to the REFCLK and sample SDI RX -> FIFO - SDI TX works. Thank!

There was another question.

The TX PLL captured CMU PLL. But CMU PLL is alone in the transceiver bank (Cyclone V GX). So, can I place only one duplex 3G-SDI channel in one transceiver bank if other banks are busy? Can I put only two duplex asynchronous SDI channels in two transceiver banks of chip?

Is it possible to implement TX PLL using fPLL or channel PLL in this FPGA family?

Are there any estimates (or rules) for the maximum number of SDI channels for Cyclone 10 GX family?

Best regards, Aleksander