SDI II IP - TX sync Issue

Hi Lim,

Thanks for your reply and help!

>Do you mean that if you connect the tx_coreclk to ExtClear_pclk, then the problem appears?

Yes. 3GSDI bitrate is (20*148.5) = 2970 Mbit/s. As far as I understand from the test results, the output bit rate on my board from transceivers is always (xcvr_refclk*20)Mbit/s. xcvr_refclk - from dedicated transceivers REFCLK pins. How do I need to connect the signals so that the bitrate is (ExtClear_pclk*20)Mbit/s?

>If the ExtClear_plck is a clean & stable clock, why not it used as refclk for SDI TX if this is coming from the transceiver dedicated clock pin?

The problem is that in one bank of transceivers I have two asynchronous SDI channels. In one FPGA there are two such banks (four SDI IO channels). There are really four ExtClear_pclk signals: ExtClear_pclk[3:0]. The task of the board is to check and pass through the input streams. All SDI channels are non-synchronous. Therefore, I need to make sure that the bitrate of each channel is (ExtClear_pclk[i]*20), where i=0..3 - is the channel number. Now all ExtClear_pclk[3:0] signals are connected via dedicated clocks inputs. These ExtClear_pclk[3:0] signals are synchronous to the bitrate of the corresponding SDI inputs, but without input jitter.

>Are you implement SDI loopback as SDI RX -> FIFO -> SDI TX?

Yes. SDI[i] RX port -> FIFO[i] (sdi_ii_ed_loopback) -> SDI[i] TX port, where i=0..3 - is the channel number.

>probably the example in alterawiki is helpful to you

I saw this page, but unfortunately links to projects on this pages do not work after the transfer to the Intel site. Where can I download the file C5gtsdi ii top.zip?

>You do not need to perform TX clock switching but the SDI II IP is still required to connect to the reconfiguration controller.

That is, the initial setup of the transceiver is still performed, even if the video standard does not change during operation?

Best regards, Aleksander