Forum Discussion

Smith222122's avatar
Smith222122
Icon for New Contributor rankNew Contributor
4 years ago

Scaler II IP Core Causing Underflow on Clocked Video Output IP

Hello there, I am having an issue with my Scaler IP core starving my Clocked Video Output (CVO) IP core and causing underflow. I think the issue stems from the scaler requiring a certain number of...
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Smith,


Thank you for your patience.

Yes I agree with Vgs, the rate is about 2 = ((1920x1080)/(1280x800)).

So the output valid signal will be asserted every two cycles.

I'm afraid the Input clock for Scalar II must be more than 124Mhz which is not included v-sync and h-sync.


Thank you.


Best Regards,

ZulsyafiqH_Intel