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Altera_Forum's avatar
Altera_Forum
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16 years ago

Sampling time and clock

Hi, I want to know the relation between Sampling time (not Simulink sample time in the clock) and clock time (Real-World clock period) option. I mean real sample time of the hardware (FPGA). How can calculate the required

time per simulation timestep for the model run on FPGA. Is Real-World clock period represent the timestep of the model?

In example the settings of the clock in my model are :

1. the Real-World clock period is 1nsec 2. Simulink sample time is 1.

Configuration parameters settings of the model are:

Start time: 1 Step time: 8000

Type: Fixed-step Solver: Discrete

Fixed-step size: 1

When the model is running on FPGA I can get results (Figure) through SignalTap II Analyzer. The x-axes is starting from 1-8000. Unfortunately I don't know how can calculate the time in sec.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    in SignalTap you have 8000 clocks at whatever your SignalTap sample clock is. for example, if the clock is 50 MHz, 8000 * 1 / (50000000) = 0.00016 seconds or 160 microseconds

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    i think you'll have some trouble trying to meet 1 ns Real World clock in an FPGA

    and i like to leave Simulink time at 1, and run the simulation for "number of samples" rather than "time". you can come across rounding errors in the self-checking ModelSim simulation with odd Simulink sample times
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thank you. if the clock is 1 ns so 1*8000= 8 microseconds. I got this result from ModelSim waveform. That mean each clock represent a sample step-time. So the elapsed time by FPGA to run the model for 8 sec is equal to 8 microseconds is it correct?