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Contributorrunning AN708 on Quartus 17.0
Hi David,
My apologies for late reply as my time is quite occupied these few days.
Thanks for your patience and the follow-up question.
Yes, the design is for hardware test rather than simulation test as mention in the user guide.
If you want to run the simulation, my suggestion is you can try to refer to the Arria 10 User guide
under section 2.1. Directory Structure and 2.4. Simulating the Design
Let me know if there is anything else that I can help you.
Regards,
Wincent_Intel
Regular ContributorHi David,
Nice to see you back. Thanks for such detail sharing.
Mind me to ask do you just purely run in simulation ? or there is any hardware connected on it ?
There is few reason why this happen
1. Simulation time is not long enough to reach the simulation end.
2. This demo project is for hardware test rather than simulation test.
Could you please confirm back in this ?
Regards,
Wincent_Intel
- dsun01
Hi Wchiah,
There is not any hardware, It purely Intel package, extract by Quartus 17.0.0.290. use platform designer open the .qsys and update the out-of-date IP. use the ModelSim - INTEL FPGA STARTER EDITION 10.5c, run the simulation.
it is not the run time problem, it is the PCIe link training no response from the DUT.
I guess the problem is this module, the output of this module
npor and pin_perst will be feed into the DUT, both of them are X.
top_inst_dut_npor_bfm_ip top_inst_dut_npor_bfm (
.sig_npor (top_inst_dut_npor_bfm_conduit_npor), // conduit.npor
.sig_pin_perst (top_inst_dut_npor_bfm_conduit_pin_perst) // .pin_perst
);Thank you,
David
- dsun01
Hi Wchiah,
Can I assume that your second statement means the simulation environment provided by the Intel development environment is not guaranteed working.
2. This demo project is for hardware test rather than simulation test.
as a learner, environment can access more detail of the core, it is easier to use than the signal tap.
Thank you,
David
