Forum Discussion
Contributorrunning AN708 on Quartus 17.0
Hi David,
My apologies for late reply as my time is quite occupied these few days.
Thanks for your patience and the follow-up question.
Yes, the design is for hardware test rather than simulation test as mention in the user guide.
If you want to run the simulation, my suggestion is you can try to refer to the Arria 10 User guide
under section 2.1. Directory Structure and 2.4. Simulating the Design
Let me know if there is anything else that I can help you.
Regards,
Wincent_Intel
ContributorMore details.
from PCIe_Link_Training_FTA_2p0
while I run the simulation,
the host bfm side rp_ltssm loop 0, 1, 2. the dut side ltssstate was always 0.
currentspeed was always 0, lane_act always 0
on the top level of testbench, there is a module
top_inst_dut_npor_bfm_ip top_inst_dut_npor_bfm (
.sig_npor (top_inst_dut_npor_bfm_conduit_npor), // conduit.npor
.sig_pin_perst (top_inst_dut_npor_bfm_conduit_pin_perst) // .pin_perst
);
these two outputs are always StX. and they feed into the npor and pin_perst of the DUT.
I guess here is the problem. this module was generated by the platform designer.
if this was the problem, please give me some suggestion how to fix this problem.
Thanks,
David
ContributorI attached archived project here.
The LTSSM toggling on the BFM side
# INFO: 161949 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 174813 ns RP LTSSM State: DETECT.QUIET
# INFO: 175149 ns RP LTSSM State: DETECT.ACTIVE
# FATAL: 175149 ns LTSSM does not change from DETECT.QUIET
but on the DUT side. LTSSM was always 0.
