Forum Discussion
Altera_Forum
Honored Contributor
14 years agoFor some reason, the whole TX MAC interface is gone post fit. All that's left of the RX side is ff_rx_data, ff_rx_eop, ff_rx_mod, and ff_rx_sop. If I look at the chip planner to see what clock is driving the rx registers, it's on Open Core clock as shown below. I don't see any messages saying that it synthesized out some of the logic. The Qsys project was based on a reference design so it looks okay. They always make it look so easy...
|GTP|pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\stratixiii_WCRO7487_gen_0:stratixiii_WCRO7487_gen_1|WCRO7487_0