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Altera_Forum
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9 years ago

Real time FIR filtering MAX 10 FPGA Development Board

Hi, I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 1...
Altera_Forum's avatar
Altera_Forum
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9 years ago

the 2,10,20,40 is ADC required clock rate for internal logic. It is not the digital data clock for fpga. I assume you will have a data clock same as sampling rate you choose