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Rleduc's avatar
Rleduc
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2 years ago

Read/Write EMIF DDR4

Hello, I'm working on Arria 10, trying to read and write data to external memory DDR4. Write part : My data comes out from a FIFO and is 16 bits wide. I need to implement a logic that can read N t...
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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
2 years ago

Hi, thank you for you answer,

I did as you mention, provide 0 data in the last burst which is not full.

Now the logic seems good, but I have the following issue :

master_write_data[255:0] is properly filled with fifo data, I can see it in signaltap. However the EMIF amm_write_data[255:0] (slave) which is directly connected to master_write_data[255:0] is equal to 0x0 ! I don't understand how is this possible, is it supposed to be the same net ?

For information, local calibartion is in success, no reset. The only thing that I can notice is that :

- waitrequest_n is always 0, so I can wait forever

- I am not sure if emif clock which is 266MHz on the DDR4 side should be the same as fifo clock which is for now 100 MHz,. Should I use the clk output from emif "usr_clk" as well as "usr_reset" to feed the fifo ? Can clock cross domain work ?

Thanks !