New ContributorRead/Write EMIF DDR4
Hello,
I'm working on Arria 10, trying to read and write data to external memory DDR4.
Write part :
My data comes out from a FIFO and is 16 bits wide. I need to implement a logic that can read N times from FIFO and write in DDR4 memory, which means through avalon-mm interface.
Since DDR4 writedata (and readdata) is 256 bit wide, "avalon-write IP" that I would implement would take 8 samples of FIFO data (8x32=256) and then write this whole 256b vector to the EMIF avalon-mm.
Read part :
For reading data stored in DDR4 from HPS, I can directly do it with alt_read_word() function and accessing it through avalon-mm bridge and H2F AXI bridge.
Issue:
I can read properly what I write in DDR4 from HPS, so this part is not of an issue. However for now, I properly read junk data, because my writing logic is wrong.
From what I understood, EMIF amm uses burst mode. A burstcount of 4 would mean writing 4 times 256b of data, which also means in my case 4x8=32 samples that came from FIFO.
If user asks for 100 samples, I feel like it will be a mess, since I can only work with a fixed number of burst (4,8,16,...1024), whose each is a fixed number of 8 samples. How do I manage the number of bursts that will in the end not exactly be related to the number of samples ? What would be the general logic ?
Thanks
