New Contributor
Super ContributorHi bob_rf,
As for modelsim, the design also comes with example test bench and TCL files to run simulation in Modelsim for reference.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\fft0\simulation\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "do wave.do" to populate the waveform
6. Type "run -all" to start the simulation
You may refer to the video link below for further details.
https://www.youtube.com/watch?v=eviC0jP90ZA
https://www.youtube.com/watch?v=e0X5KMVt4F8
Best regards,
Sheng
New ContributorHi Sheng,
This is a reply to your two most-previous posts to me.
Regarding your earlier post about removing db and increment db folders, while ensuring settings -> simulation tool -> set to none:
This looks to have worked and allowed the project to be compiled.
Regarding your second/later post to me about using ModelSim, I followed your steps and was able to run the .tcl file and generate the FFT ports which can be added to the waveform window.
As you can see from the picture, this is definitely progress from the vsim 3033 error I was stuck on.
I have a couple of questions:
*Is it possible to simulate my overall design, in Evaluation Mode, which uses the FFT IP? Or am I only able to simulate 1 instance of the FFT IP at a time, and only this 1 instance (not other design elements of a project)?
*I have used search engines and searched through directories on my work computer, but I am not sure where the "example test bench" you mentioned (for FFT IP) is included or available for download. I was able to run the .tcl script you mentioned because I found one by the same name in my instantiation of the FFT IP, but I could never find the folder to unzip which you mentioned. Can you tell me where I can find this example test bench file?
Also, I need to make sure when I call the .tcl file that the testbench will supply the simulation inputs. Is there an extra step or edit I need to make to the .tcl file to supply the input simulation data?
Regards,
Robert
Super ContributorHi bob_rf,
You may refer to the video links below for further details.
https://www.youtube.com/watch?v=eviC0jP90ZA
https://www.youtube.com/watch?v=e0X5KMVt4F8
Go to Tools/Generate Simulator Setup Script for IP... to produce combined qsys and ip simulation scripts.
**Note: This feature is available in the Intel Quartus Prime Pro Edition software for all devices.
This feature is available in the Intel Quartus Prime Standard Edition software for only Intel Arria 10 devices.
Follow video to create do file as below. Your testbench can be included in do file.
--- Quote Start ---
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
--- Quote End ---
Modelsim native link still fails even after no error compilation?
Best regards,
Sheng
