Queries on 46.6944 Gbps PAM4 F-Tile Configuration and Loopback Testing using Agilex7

Hi,

As I understand it, you have several inquiries related to BER performance on the F-Tile Transceiver. Let me address them one by one.

Regarding your observation that the external loopback shows a non-zero BER while the internal loopback reports zero BER, this is expected behavior. In internal loopback mode, the transmitted data is looped back to the receiver within the transceiver itself, bypassing the external channel. As a result, the signal is not exposed to any external signal integrity impairments such as channel loss, noise, crosstalk, or reflections.

In contrast, external loopback exercises the complete signal path, including the PCB traces, connectors, cables, and other channel components. Therefore, any signal integrity degradation along the external path may contribute to bit errors and result in a non-zero BER.

By the way, I was unable to locate the test design and Transceiver Toolkit results that you referenced. It is possible that I may have missed them. Could you please point me to the relevant files or share them again for review?

Please let me know if you have any concerns or additional questions. Thank you.