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New Contributor

17 days ago

[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration process

Hello, I am trying to simulate with questa fe the pcie design example (with pipe mode for external dma controller) based on agilex7 generated with quartus pro 25.3.0 but i am facing these issues whe...

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Frequent Contributor

7 days ago

Hi Frederic,

Are there any updates on my previous message?

Thanks.

Best Regards,

Ven

FGR1
New Contributor
7 days ago
Hello and thanks Ven for answering to my issue.
Yes i confirm that we are using F-Tile MCDMA IP with Data Mover Only option.
I am using Questa Altera FE edition (associated to the Quartus Pro version 25.3.0).
I will try to remove the PIPE mode by using only serial simulation and will get you back soon.
Is there any chance to get a simulation with the above options (Data Mover Only) with a new quartus pro version ?
Regards,
Frederic
- VenT_Altera
  Frequent Contributor
  4 days ago
  Hi Frederic,
  
  Thank you for the update.
  The Questa Altera FE edition simulator is unlikely to be supported for simulation of the Data Mover Only - External Descriptor Controller Example Design) in future Quartus version. It is recommended to use the full version of QuestaSim to run the simulation, which is supported in Quartus Prime Pro Edition v25.3.0. When using the full version of QuestaSim, you may enable the PIPE option to accelerate the simulation.
  
  Additionally, the vsim-3008 and vsim-3043 errors you encountered previously with PIPE mode enabled can be resolved by switching to the full version of QuestaSim. Please note that you may also need to apply the suppress 2732/10000 workaround described in the KDB (https://community.altera.com/kb/knowledge-base/why-does-simulation-of-the-f-tile-multi-channel-dma-fpga-ip-for-pci-express-erro/338491) before proceeding with the simulation.
  
  Thanks.
  Best Regards,
  Ven