GTS Reset Sequencer IP o_refclk_on_ack

Hi,

For your information, I checked the GTS Transceiver PHY User Guide for a minimum pulse width specification on o_refclk_on_ack. Unfortunately, I could not find any documented minimum pulse width requirement for this signal in the available documentation. As a result, I am unable to confirm whether a 100 MHz sampling clock (10 ns period) can reliably capture the pulse under all conditions.

Given this uncertainty, I would recommend the following approaches:

1. Use edge detection as a robust design practice
2. Instead of directly sampling o_refclk_on_ack with the system clock, consider implementing an edge-detection circuit and synchronizing the detected event into your clock domain. This helps avoid missing a narrow pulse.
3. Verify the pulse width through simulation
4. Run functional or timing simulations to observe the expected pulse width of o_refclk_on_ack and determine whether it can be consistently captured by a 100 MHz clock.
5. Measure the signal in hardware using Signal Tap
6. Capture o_refclk_on_ack with Signal Tap to verify its pulse width and behavior in the actual device implementation.
7. 
   

I hope this helps. Please let me know if you have any further questions or need additional assistance.

Thank you.