GTS PMA/FEC Direct Transceiver Streaming

Hi,

Sorry about the image display issue. I am trying to refer the following section "6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design" as in the GTS Transceiver PHY User Guide: Agilex 5 FPGAs and SoCs user guide. I extract some of the texts from the user guide as following. You may double check on the commenting out specific 2 lines in the .qsf file.

"You can perform hardware testing of the example design on the Agilex 5 FPGA ESeries

065B Premium Development Kit (ES1) board. You must select this

development kit in the Select Board setting in the Example Design tab of the IP

GUI, so that the reference clock and channel pin assignments are generated for the

development kit’s hardware design by the Quartus Prime software in the .qsf file.

If you require to change the pin assignments of the example design, you can comment

the following lines in the example_design.qsf file.

#set_global_assignment -name POST_MODULE_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

#set_global_assignment -name PRE_FLOW_SCRIPT_FILE

"quartus_sh:board_assignments.tcl"

After you have commented out the lines, you can set the pin assignments according to

your board setup and the assignments are reflected in the example design."

Please let me know if the issue still persists after you tested the above.Thank you.