Forum Discussion
New ContributorGPIO DDRIO IP output swapped: datainhi/datainlo inverts forwarded clock
Hello Paul,
We have checked the design. We think it may be because of your coding design. We switched your 10 to 01 and got this result. Is this what you are expecting?
Image 1: Waveform
Image 2: Design
Image 3: Reference from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf
Thank you.
Regular ContributorHello,
The last screenshot you've given is on Guideline: Swap datain_h and datain_l Ports in Migrated IP which is for migration for your GPIO IP from previous devices to the GPIO IP core. This only applies only for the migration.
New ContributorAmin,
I am grateful for your assistance in resolving this issue: all of our cyclone10gx_ddio_out instances are working properly now in our FPGA design. I accept that I have misunderstood the documentation and that the GPIO IP is working as Altera designed. I'd suggest, though, that it would be helpful if someone added a full-rate scenario timing diagram to the docs, because the IP does behave differently than the legacy altddio_out megafunction with nearly identical port names. At the very least, this thread will be here if anyone else is snagged.
Best regards,
Paul
- AminT_Intel
Hello Paul,
I'm glad that it helps! Thank you for the suggestion we will take note of that.
Thanks
- AminT_Intel
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
