New Contributor
Frequent ContributorHi,
Are you following the same timing diagram(as mentioned in the link below) as per your mode?
Thank you
Kshitij Goel
New ContributorHi,
actually the system is composed by Platform Designer, and all the read accesses are made by a Nios II processor.
The read access is simply done by a predefined IORD(), as per all the other MM slave in the system that works correctly.
So I expect this IORD follow the correct timing diagram.
Unlucky reading the one coefficient at first address deadlocks the processor that stop works. Otherwise everything works correctly.
Any ideas?
