Forum Discussion
New ContributorFailed driver initialization of Serial Flash Controller II Intel FPGA IP
Hi Sheng,
I have received some information regarding this topic from another end. An acqaintance of mine contacted the Intel support directly and just heard back from them.
Here's the answer he received:
There is a mistake in the Platform Designer for the "Serial Flash Controller II"
The "Serial Flash Controller II" IP does not support external flash such as Micron.
If you refer to the document located here:
https://www.intel.com/content/www/us/en/docs/programmable/683130/22-2/configuration-device-types-85589.html
Somehow there is a bug in the platform designer for the "Serial Flash Controller II" that the drop down list showed other flash option than intended.
The correct IP that the customer should use is the "Generic QUAD Flash Controller II".
If you see the code, there is a shift of 2 bytes to properly read the "memory capacity" byte instead of the device ID.I verified his suggestion to use the "Generic QUAD SPI Controller II" instead. Now it gets initialized automatically in alt_main() like a charm.
Thank you for your effort!
Best regards
Dominik
New ContributorHi Sheng,
Your suggestion to alter the define ALTERA_EPCQ_CONTROLLER2_DEVICE_ID_DATA_0_REG did not work for me, I'm afraid:
And from what I understand, this define is only the offset for the DEVICE_ID_DATA_0 register.
When looking into the Register Memory Map (20.2.1. Register Memory Map (intel.com)), though, I find the DEVICE_ID_DATA_0 offset being 0x8 rather than 0x20. If I change the define ALTERA_EPCQ_CONTROLLER2_DEVICE_ID_DATA_0_REG to 0x8 instead of 0x20, the initialization seems to succeed.
Yet, this is not the only register where this kind of mismatch occurs between the alter_epcq_controller_2_regs.h and the Register Memory Map: FLASH_MEM_OP is 0x3 on intel.com, yet 0xC in the code; FLASH_CHIP_SELECT is 0x6 on intel.com, yet 0x18 in the code. Apparently, all the registers are left-shifted by 2 bits to what intel.com says they would be. Why is that?
So at this point, there are three possibilities, the way I see it:
- The shifting of the register offsets is incorrect and manually correcting them in the altera_epcq_controller2_regs.h would be a short-term workaround until the root of this behavior is fixed. This would not be ideal, to be honest, since this needs to be done every time the BSP has been generated and can easily be overseen.
- The success in initializing the flash controller by altering the register offset to 0x8, I described above, was a mere coincidence and the actual problem is, that the initalization state of the register DEVICE_ID_DATA_0, which in this scenario would be correctly addressed by the offset 0x20, is not correct, in that it should not be 0, as altera_epcq_controller2.c, line 589 (see screenshot above) implies.
- Points 1 and 2 are both incorrect and I am missing something.
Any thoughts?
Best regards,
Dominik
