User1580871742356367
Occasional Contributor
Occasional ContributorEMIF controller and DDR4
Like to confirm who's programming the DDR4 MMR registers.
The Memory controller engine alone(without SW or SW (e.g. uboot etc.) ? Thanks.
Forum Discussion
SimonRichterOccasional Contributor
Occasional ContributorThe initial configuration is done by the memory's sequencer block, from the IP settings, so in the simple case, you don't need to use this interface at all and you can disable it.
U-Boot could use these registers during a memory test, and the operating system could use those registers to detect ECC errors at runtime, so if that is desired, you'd connect the interface to the soft CPU's data bus.
