Cyclone IV GX PCIe Hard IP behaves differently on Intel Core I7 vs Xeon root complexes

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Hi Wincent_Altera​,

Let me clarify my observation.

When a PCIe read or write transaction occurs, SignalTap captures the transaction correctly and I can see the expected activity and data values.

However, only for a short period after the transaction. A few moments later, the observed data bus returns to 0xFFFFFFFF (all bits = 1) again.

In other words, the correct value is visible only while the transaction is active and captured by SignalTap. After that, the signal returns to its default state of all 1's.

Because of this, it appears that the driver is reading 0xFFFFFFFF, while SignalTap shows the expected value during the actual transaction.

Is 0xFFFFFFFF the expected idle/default value on the Avalon-MM read data interface when no valid read response is present, or could this indicate a completion/read response issue?

I have already forced the PCIe link speed to Gen1 and confirmed successful Gen1 x1 link negotiation. The behavior remains the same.

Could you also let me know which PCIe driver/test application is used for Cyclone IV GX PCIe validation?

Regards,
Umesh Sharma