Occasional Contributor
New ContributorHi Richard,
First thank you for confirming the issue. I'm glad it has been noted, but I don't think it's isolated to release 25.1. Perhaps it's bad luck, but I have not been able to get reliable operation with it for a Max 10M08SAE in Quartus 17.1, 23.1 or 25.1. I've tried two different systems... 1x AMD, 1x Intel, both running Windows 11 with 4k monitors. The behavior changes between releases, but every instance involves a scrambling of the screen due to GUI sizing and overlayed text. Unlike 25.1, 23.1 was marginally readable.
I did read about issues with high-resolution displays which lead me to testing the compatibility settings and hi-res override modes. This leads me to the reason I believe the issue has been there awhile... the graphics compatibility settings changes the Megafunction behavior. In some modes it refused to open, while in others it would open and crash. The only setting that allowed it to open was no setting. There isn't a great reason why changing this should cause such a dramatic shift in behavior.
I would appreciate it if Altera could post an app note on how to instantiate a basic PLL without the Megafunction... a bare minimum implementation (1 clock in, 1 clock out). I don't mind configuring a slew of parameters, I just want something that works and I can modify without worrying about the software version I have installed or having to jump between versions.
Thanks!
Super ContributorHi,
VHDL example, inclock 16 MHz, outclock 50 MHz
library ieee;
use ieee.std_logic_1164.all;
entity plltest_min is
port
(
inclk0 : in std_logic := '0';
c0 : out std_logic
);
END plltest_min;
architecture inst of plltest_min is
component altpll
generic
(
bandwidth_type : string;
clk0_divide_by : natural;
clk0_duty_cycle : natural;
clk0_multiply_by : natural;
clk0_phase_shift : string;
inclk0_input_frequency : natural;
operation_mode : string;
pll_type : string;
compensate_clock : string := "CLK0";
self_reset_on_loss_lock : string
);
port
(
inclk : in std_logic_vector (0 downto 0) := (others => '0');
areset : in std_logic := '0';
clk : out std_logic_vector (0 downto 0);
locked : out std_logic
);
end component;
begin
mypll : altpll
generic map (
bandwidth_type => "AUTO",
clk0_divide_by => 16,
clk0_duty_cycle => 50,
clk0_multiply_by => 50,
clk0_phase_shift => "0",
inclk0_input_frequency => 62500, -- 16 MHz
operation_mode => "NORMAL",
pll_type => "AUTO",
self_reset_on_loss_lock => "ON"
)
port map (
inclk(0) => inclk0,
clk(0) => c0
);
end inst;Verilog example
module vpll_min (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] clk;
assign c0 = clk[0];
altpll altpll_component (
.areset (1'b0),
.inclk ({1'b0, inclk0}),
.locked (),
.clk (clk));
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 16,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 50,
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 62500,
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmoduleRegards
Frank
Occasional ContributorThanks Frank, That is very helpful, In my case i need to instance the ALT_PLL with all four of the clocks enabled in System Verilog (or Verilog). I would like to do that using the 'Set Frequency option' method as well and not the multiply / divide by method. With the following setup: The PLL Input frequency is 25 MHz, then i need to set the PLL output clocks c0 to c3 as follows:
c0 -> 100 MHz
c1 -> 5 MHz
c2 -> 50 MHz
c3 -> 125 MHz
Can you please provide me with an instantiation template as you did for the previous case ?
Thanks very much,
Barry
Super ContributorHi Barry,
unlike altera_pll (e.g. used for Cyclone V) altpll IP doesn't accept MHz values.
You can however add arbitrary integer multiply_by and divide_by values, e.g. assuming 1 MHz reference frequency. They are automatically converted to appropriate PLL parameters. Also input frequency should be specified in ps.
module vpll_min (
inclk0,
c0, c1, c2, c3);
input inclk0;
output c0;
output c1;
output c2;
output c3;
wire [4:0] clk;
assign c0 = clk[0];
assign c1 = clk[1];
assign c2 = clk[2];
assign c3 = clk[3];
altpll altpll_component (
.areset (1'b0),
.inclk ({1'b0, inclk0}),
.locked (),
.clk (clk));
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_multiply_by = 100,
altpll_component.clk1_divide_by = 25,
altpll_component.clk1_multiply_by = 5,
altpll_component.clk2_divide_by = 25,
altpll_component.clk2_multiply_by = 50,
altpll_component.clk3_divide_by = 25,
altpll_component.clk3_multiply_by = 125,
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmoduleRegards
Frank
Occasional ContributorHi Frank,
Thanks very much for your help. Its a bit strange though because on editing the corrupted diagram for the intel ALTPLL IP version i can select the 'Set Frequency' tab for all of the 5 clock outputs and it lets me put in a frequency. I have to keep switching on and off a different TAB on the IP core GUI to see it clearly (only temporarily). But i am able to set frequencies.
