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shashwatss's avatar
shashwatss
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26 days ago

Agilex-5 supported Transceivers

I am currently evaluating the capabilities of the Altera Dev Board DK-A5E065AB32AEA. As most SFP+ and QSFP+ Transceivers are often vendor-locked, is there a list of qualified Transceivers available?...
Transceiver
shashwatss's avatar
shashwatss
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13 days ago

Hi,

sure. The issue was observed at the first start-up of the dev kit. The kit comes pre-programmed with an HPS Image, and this image was used for the initial testing as per the document D554638(published date 2026.06.19)
I downloaded the development kit files as per point 2.3.2 of the document. Below mentioned is the case for QSFP28. Similar steps were also performed for SFP28. 10G SFP+ was attempted as well.

  • Path is \*\Altera_Devkit_design_package\DK-A5E065AB32AEA-26.1.0.104\examples\board_test_system\
  • start.batch was launched with admin rights
  • Clicking Agilex-5(as per Fig.8 in document) launches Figure 38.
  • Navigating to point 4.3.5.3 -> issue with QSFP28 design. Programmer crashes with message "failed"
  • The above screenshot is for *.sof* of DDR, but similar was for the case of QSP28 as well as SFP28 as well
  • Therefore, BTS GUI was closed. And Altera FPGA Programmer was used for loading the *bts_qsfpn.sof* file located at \\Altera_Devkit_design_package\DK-A5E065AB32AEA-26.1.0.104\examples\board_test_system\image\sm72si\PRD0\
  • Once the sof loads successfully, BTS GUI is launched again. Clicking on Aglilex-5, shows the current configuration of the board. 

  • Attaching a 100G XCVR and cable for loopback - in the above case, we used the 100G Transceiver which is supposed to be compatible to Nvidia Mellanox. - Did not work. Tx at 100% and Rx at 0%.

  • Next, we used 40G QSFP+ Xcvrs which are "generic" - the exact meaning of such a transceiver is unknown-( dunno which vendor code was written in the EEPROM for i2C comm)
  • I repeated such a test-setup  for both the 25G and 10G transceivers, and tried using with BTS.
  • Sadly, I ordered all transceivers as Nvidia compatible and hence we it did not work as mentioned above.

All transceivers were purchased from FS.COM. Exact product is SFP-25GSR-85,  QSFP-SR4-100G

Hence, the query to inquire about the exact hardware components used by the board manufacturers to qualify the design on their end before shipment.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
10 days ago

Hi,


Thank you for the update. To facilitate further debugging, I recommend using the XCVR Toolkit, or alternatively a simple XCVR design with SignalTap, to monitor the transceiver status. The XCVR Toolkit would be the quickest approach to get started.


Please follow these steps:

  1. Generate an example design using the GTS PMA/FEC Direct PHY IP and target the relevant development kit.
  2. Select a simple configuration from the available example design options, preferably using a single channel and a lower data rate.
  3. Enable the XCVR Toolkit by following the instructions in the GTS Transceiver PHY User Guide, under the “GTS Transceiver Debugging Flow Walkthrough” section.
  4. Assign the transceiver pins to the SFP+ interface.
  5. Compile the design and program the resulting SOF file onto the development kit.
  6. In the XCVR Toolkit, enable internal serial loopback and monitor the TX and RX lock/status indicators.
  7. Run the PRBS test with internal serial loopback enabled. This will help verify the basic transceiver functionality without depending on signal integrity or an external loopback connection.
  8. Disable internal serial loopback, plug in the SFP+ module, and repeat the test.

Please share the observations from both tests, including the TX/RX lock status, PRBS test results, and any reported errors.


Please let me know if you have any questions.