Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorRam memory read 2 cycle delay
I use Memory compiler in MeagWizard to generate 1-port Ram. but there are both one register at input and output, this make read delay 2 cycle. I want to know if there is anyway to make Ram...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- On the latter pages, there should be option to disable registered outputs. --- Quote End --- omg haha thanks I knew that I must be missing something :p
