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Altera_Forum's avatar
Altera_Forum
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13 years ago

Ram memory read 2 cycle delay

I use Memory compiler in MeagWizard to generate 1-port Ram. but there are both one register at input and output, this make read delay 2 cycle. I want to know if there is anyway to make Ram...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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On the latter pages, there should be option to disable registered outputs.

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omg haha thanks

I knew that I must be missing something :p