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Altera_Forum
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13 years ago

Questions about SGDMA's IN connected to Avalon-ST Dual Clock FIFO.

If SGDMA(Stream to Memory)'s IN is connected to Avalon-ST Dual Clock FIFO's out,the there are SOP,EOP signals built in SGDMA IN port. The SOP,EOP inside SGDMA IN port is INPUT attributes,and the D...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thank you Xiwen!

Sorry for I'm a greenhand in FPGA,I still have some questions.

You mean that the SOP/EOP in the INPUT port of DC_FIFO will be sent to OUTPUT port of DC_FIFO at the same time transparently without any change?

So,

If DC_FIFO receeives a data with its packet size is 0x2000 for example,and SGDMA reads 512 bytes data from DC_FIFO to send to PCIe IP each time.

The SGDMA just reads 512 bytes data from DC_FIFO as when the SOP of DC_FIFO is high and EOP of DC_FIFO is low,and when the reading operation is end,

I mean that SGDMA have read 512 bytes data,the SGDMA can end the operation by itself,and do NOT have to wait EOP signal is HIGH?

Best Regards~