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lipingx
Occasional Contributor
Occasional Contributorquestion for design example of Intel fifo IP
In this example, rom_out, wrreq_o, wrclk are using the same clock trclk.
All above are trigger by rising edge of trclk.
But the fifo write are also refer to rising edge of trclk.
So if there i...
Yes, you can shift the wrclk to 180 degree which can meet timing. There is no saying you can not do that.
Best Regards,
Richard Tan
lipingxOccasional Contributor
Occasional ContributorI believe so, intel IP should be correct. But can you explain a little on it?
Why not move the wrclk to shift 180 degree which may perfectly meet timing constraint?
The clock wrclk rising edge will stay in the middle of fifo_in data.
