Forum Discussion
lipingx
Occasional Contributor
Occasional Contributorquestion for design example of Intel fifo IP
In this example, rom_out, wrreq_o, wrclk are using the same clock trclk.
All above are trigger by rising edge of trclk.
But the fifo write are also refer to rising edge of trclk.
So if there i...
Yes, you can shift the wrclk to 180 degree which can meet timing. There is no saying you can not do that.
Best Regards,
Richard Tan
RichardT_altera
Super Contributor
Super ContributorMost Intel IP has been designed to meet timing. If you worried, you can run the timing analysis stage and the Quartus will analysis and place&route the design as best as possible in order to meet the timing. If there is timing violation, we will see red flag in the timing report.
Best Regards,
Richard Tan
