Forum Discussion
lipingx
Occasional Contributor
Occasional Contributorquestion for design example of Intel fifo IP
In this example, rom_out, wrreq_o, wrclk are using the same clock trclk.
All above are trigger by rising edge of trclk.
But the fifo write are also refer to rising edge of trclk.
So if there i...
Yes, you can shift the wrclk to 180 degree which can meet timing. There is no saying you can not do that.
Best Regards,
Richard Tan
FvM
Super Contributor
Super ContributorHello,
the design example is based on standard synchronous logic design methods. It expects that all modules operating in a clock domain are clocked by the same clock source and sampling at the same edge. Design implementation and timing analysis guarantee that all register input signals achieve necessary setup and hold times.
You get highest logic speed by clocking all register at the same (usually risng edge). Register hold time is smaller than the "natural" data path delay, if not timing driven synthesis would enforce it.
