JET60200Contributor4 years agoquestion about “ A10SOC as PCIE RC ” hello expert, We plan to start an “ A10SOC PCIE RC” design, while the peer side PCIe EP is a "pcie subcard w/ (gen3x8)". Our target is to run Linux System on this A10SOC (HPS), and use HPS AR...Show More
Recent DiscussionsError when simulating F-tile Ethernet example designAvalon Transaction Responses & BridgesSerialLite II license for Arria10 FPGAAgilex3/5 GTS Hard Ethernet IP 10G example design pin loc and io std wantedCORDIC ATan2 Failed to Generate