QSYS amm interconnect delay with EMIF (Arria 10)

That is odd. In PD, hover your cursor over the connection dots between the controller and EMIF IP to see if there is additional conversion logic being inserted due to some mismatch between the two sides. The tooltip will indicate as such and may clue you in to why this is happening.

You could also try adding Signal Tap to the design and tap into the interconnect to see what may be happening.