New Contributor
Regular ContributorHi,
This warning occur due to reason specified in the following link:
Please note the difference between the two modes:
• Direct mode—the PLL minimizes the feedback path length to produce the smallest possible jitter at the PLL output. In this mode, the PLL does not compensate for any clock networks.
• Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network.
As Direct mode does not have any feedback path, the warning will not occur for that mode. It make sense only for the Normal mode. Action to be taken as specified in the above link.
Regards
New ContributorHi,
Thanks for the reference. However, I'm a bit confused as to the best way to reduce the feedback path length: how is that calculated, and what do I need to do in order to reduce it? We're connecting the PLL to the IP and our user logic. Should we be using a different clock for our user logic?
More specifically, what is the proceedure for determining the length of the feedback path, and how does one reduce the feedback path length?
