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Altera_Forum
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11 years ago

Problems with PCI express IP Compiler and Pin Planner

Hi, I began to study PCI Express system in order to implement on a FPGA. I'm using Stratix II GX development Kit board and i already am at the point to connect the pins of the FPGA using the Pin Plan...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

First, you need refer to Figure 5–41 of IP Compiler for PCIe User Guide to understand the PCIe Rx/Tx transceiver channels location assignments.

The assignment is like this:

Transceiver Ch0 --> PCIe Rx0/TX0

Transceiver Ch1 --> PCIe Rx1/TX1

Transceiver Ch2 --> PCIe Rx2/TX2

Transceiver Ch3 --> PCIe Rx3/TX3

... and so on

The refer to the Stratix II device pin-out files to know the pin location assignment.