Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorProblems getting the PCIE BFM to work with 125MHz reference clock
Hi, I have been trying to test a design using Avalon ST Stratix V PCIE Hard IP with a 125MHz reference clock. I tried building the BFM and it seemed to work, but when I siumulate it I get warni...
Altera_ForumHonored Contributor
Honored ContributorBelow are the changes needed to run the simulation at refclk 125MHz:
1. Open the .qsys, select refclk 125 MHz in the Avalon-MM Stratix V HIP for PCIe. 2. Connect the clock output from the Clock Source to refclk input of PCIe core in Qsys. 3. Hit 'Generate testbench system' to generate the testbench, then re-run the simulation.
