MSenk1
New Contributor
6 years agoProblem with IP core Plus
I do have a design that works fine with Intel Open Core Plus and time-limited .sof files.
Now I generated a new revision and changed the device to a device that fits my demo board from10CX150YF672E5G to 10CX220YF780E5G.
Now no .sof file is generated any more and I see this warning:
Warning(18390): Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design.
How can I get a time-limited .sof file again? I found no setting for 'Simulation-Only'.
regards
Mike