Altera_Forum
Honored Contributor
14 years agoproblem with input block and also replace_block question
i am brand new to DSP builder, to be honest even to concepts in dsp also...and really have only taken one course in signal processing...
i constructed the model attached as per the handbook on FIR compiler, from DSPbuilder vol 2. i don't understand why my signal after the dsp-builder input block is not showing up on the input scope 3. shouldn't the signed fractional specification for 3 bits with length of 8 good enough? what am i doing wrong? i feel as though i am lost on this problem. the signal sources: sine source: sample time : 1/1e7 freq @ 500MHZ Random Source: sample time: 1/1e7 the other question that i have is (this is more a simulink question): how would i refer to dsp-builder block or library if i want to replace a bunch of multipliers and adders that were generated with FIRtool from matlab. the replace_block syntax: replace_block('sys', 'old_blk', 'new_blk') would have to be directed towards the new dsp builder blocks that are to replace simulink blocks. what's the correct syntax for that? thanks for the help By the way the specs for the filter are : LP cutoff @ 1.25MHz Sampling...at 10MHZ these are default values... i didn't even change them from the compiler settings when i opened it up. sorry i am having trouble uploading on altera's servers. i will try to do it later from home