Forum Discussion
MSenk1
New Contributor
New ContributorProblem with EMIF IP and the related clocks in the .sdc file
I have instantiated a EMIF IP in Quartus 19.4. Alle emif clock are generated as the timing analyser shows (see attachment. But when I set a false path in the .sdc file for such a clock I get the fo...
sstrell
Super Contributor
Super ContributorAs you state, you should use asynchronous clock groups. This cuts the paths between the clock domains, through the FIFO, not the clock paths themselves:
set_clock_groups -asynchronous -group usr_clk -group <clock on other side of FIFO>
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