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EvanHamiltonJAVS's avatar
EvanHamiltonJAVS
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2 years ago

Problem W/ Altera VIP Frame Buffer II

I have configured an FPGA design for my linux device that is displaying SDI and HMDI inputs. It was originally configured to receive YCbCr 4:2:2 video format. Since I am experiencing green spill on i...
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KianHinT_altera's avatar
KianHinT_altera
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2 years ago

Hi Evan,

The team here is asking for more information on what are the base addresses are and the associated settings in the 4 frame buffers? In addition, did you do any maximum bandwidth calculations to check that the EMIF can service all 4 frame buffers at the same time if required?

Thanks

Regards

Kian

EvanHamiltonJAVS's avatar
EvanHamiltonJAVS
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2 years ago

Hey Khtan,

The frame buffer's base addresses and associated settings can be seen in the DTS snippet I provided:

In this DTS file image you can see the virtual base addresses, max width and height, bits per symbol, and port width.

Here you can see the frame buffers initializing to their physical addresses:

The EMIF has had no issues before handling all 4 frame buffers, but since I have changed the video format from YCbCr to RGB I guess that could be surpassing the maximum bandwidth. How would I conduct those calculations to check if the EMIF can handle all 4 frame buffers with RGB?

Thanks,

Evan

evanh@javs.com