problem sending mem write TLPs using PCIE core

Look at the pcie user guide (http://www.altera.com/literature/ug/ug_pci_express.pdf). Table 5–4 specifically says about tx_st_valid<n>:

--- Quote Start ---

Clocks tx_st_data<n> into the core. Between

tx_st_sop<n> and tx_st_eop<n>, must be asserted if

tx_st_ready<n> is asserted. When tx_st_ready<n>

deasserts, this signal must deassert within 1, 2, or 3

clock cycles for soft IP implementation and within 1 or 2

clock cycles for hard IP

--- Quote End ---

So you have to read it that way: Must not be de-asserted during a packet transmission, except when the hard IP indicates flow control by de-asserting tx_st_ready<n>.

– Matthias