problem sending mem write TLPs using PCIE core

You are not allowed to deassert tx_valid during your whole packet, you have to stream it to the hard IP TX port at once. The only situation where you have to stop is when tx_ready is de-asserted. This means that you either have to be prepared to do the streaming at full 64 bit I/F width from your data source or you need some kind of intermediate buffering and only start the transaction when you are prepared for a sustained data rate.