Occasional ContributorProbelm with the simulation wave form of my counter fifo
I am opening this new thread based on the suggestion from the intel community help. If you feel some more information needed please refer the message thread (please click here).
I was trying to simulate my design that is created using Platform Designer System. I have a counter module counter.v which is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. But the simulation waveform outputs of the counter.v and counter + Avalon FIFO IP looks different. (please see attachments Capture_wave_counter.PNG and Capture_wave_counter_fifo.PNG)
When I simulate just counter module (using counter_tb.v, that I attached in previous message thread message) the wave form of the data output (avalon_data) behaves as normal (have starting value 00000000000000000000000000000001) and starts the data with 32b'1 (please see attached Capture_wave_counter.PNG). But at the same time, when I simulate the counter_fifo with the testbench counter_fifo_tb.v . The fifo_0_out_readdata looks something different than the and the first entry is `00000001000000000000000000000000` (looks like counting started from the 8th bit. Please see the picture Capture_wave_counter_fifo.PNG). Also please see Counter_fifo_wave_1.PNG
Is it something to do with the FIFO parameter setting? You can see from the Counter_FIFO/counter_fifo.qsys file the parameters I used (also see the attached counter_fifo_qsys.PNG). I am just wondering that setting channel width parameter =8 in Avalon-ST Port settings of FIFO IP has to do something with this? (as you can see in counter.v, there is no signal named "channel" defined in it). I read from the FIFO IP manual that 'channel" signal is not mandatory one, and would like to make sure that the did not make any difference here.
The working directory is attached as Counter_FIFO . It contains counter.v and counter_tb.v for simulating just counter module . For simulating counter fifo design please see ../Counter_FIFO/counter_fifo/sim/counter_fifo_tb.v and the .do file used for the simulation is ../Counter_FIFO/counter_fifo/sim/mentor/sim.do
(I compiled the whole design in Quartus Prime Pro and using Arria 10 device. To get the counter fifo design, I have added the counter custom IP and Avalon FIFO IP in the IP in the Platform Designer)
