Probelm with the simulation wave form of my counter fifo

Sorry for the delay in response.

I believe the "channel width" parameter in the Avalon-ST port settings of the FIFO IP can potentially cause the simulation waveforms of the counter module and the integrated counter + Avalon FIFO IP to appear different.

The "channel width" parameter determines the width of the data channel in the FIFO, specifying the number of bits in each data element that can be read or written. If the channel width is set differently between the counter module and the FIFO IP, it can result in misalignment or reinterpretation of the data.

In your case, as the counter module produces 32-bit data but the FIFO IP's channel width is set to 8 bits, the FIFO will treat the 32-bit data as four separate 8-bit data elements. This can lead to the waveform discrepancy you observed, where the FIFO output starts counting from the 8th bit instead of the first bit.

Hope that helps to explain.

Btw, I have trouble duplicate the simulation, could you help to provide the simulation flow/steps/script to replicate it?

Best Regards,

Richard Tan

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